HDL Code Checking

Static HDL code analysis

Particular for VHDL it can be noticed that its origin is a hardware description language. It was not intended to be used as an implementation language but as a result of the emerging synthesis tools the HDL languages ( VHDL, Verilog) were used for implementation purposes as well. This results in problems because not all parts of the description can be synthesized meaningful.
Sole compiler normally are only able to detect syntactical failures, hence bad semantic will be identified to late (during or after synthesis) or never. In praxis it might take a good deal of designers time to find the reason for the unpredictable behave or even worth the behave of the synthesized circuit does not match the simulated model at all.

Static analysis (Lint) tools helps to locate HDL models with poor or inappropriate code style still during the compilation. The designer will be advised that the modeling can causes problems. The usage of Lint tools results in a higher code quality and improves the design flow.
Companies with the requirement of a certified design flow need static analyses tools to document and control the design process quality.
Static analysis capability can be added as low cost into integrated design environments or as a complete, separate configurable tool which one can find mostly at an higher price point.

Lint Optionen in ActiveHDL

Integrated tools (like Active HDL) often allows the selection of different rules sets