FPGA Design Flow

Preface

FPGAs usually are developed by using a hardware description language like VHDL and/or Verilog. While in US and partly in Asia Verilog is dominating, in Europe VHDL is mostly in use. Modern design flows supports in principle both languages hence you can combine them in a project. The mixture of the languages makes often sense when the design is described in VHDL but the IP blocks are described in Verilog. This is a typical scenario in Europe.

Generic design flow

The following steps are in accordance with the proceedings for FPGA design:

• Design entry (eventually with Code Checking)
• Functional simulation
• Synthesis
• Implementation
• Design Verification
• Debugging
• Prototyping (optional during the development phase)

Hersteller-unabhängiger Design Flow in Active HDL

Technology independent design flow in Active HDL

An integrated design environment offers an automated design flow. Tools which are vendor independent in principle can be used for design entry and simulation of all vendor technologies. Instead of a flow for each vendor a unique environment is available. Vendor specific tools for logic synthesis and place and route can be seamless integrated.