Large FPGA and ASIC Verification

Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. Riviera-PRO includes advanced debugging tools and support of advanced verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking. Riviera-PRO works in command line mode and in GUI with easy switching between the two.

Top Features

• Common-Kernel VHDL, Verilog®, SystemVerilog, SystemC/C++/TLM 2.0 Simulator
• 32 and 64 bit simulation
• SystemVerilog, PSL and OVA Assertions and Functional Coverage
• Code Coverage: Statement, Expression, Condition, Branch, Toggle & Path
• Unified HDL/SystemC code level debugging
• Accelerated Waveform Viewer
• VHDL and Verilog Code Checking (Lint)
• Fast, kernel-level co simulation with MATLAB®
• Script compatible with other HDL simulators
• Linux and Windows® 7/Vista/XP/2003 32/64 bit support

Product Training
Technical Documents

Related Technologies

Verification

• VHDL Simulation

• Verilog Simulation

• SystemC

• SystemVerilog

• Assertions

• Verilog Simulation Optimization

• VHDL Simulation Optimization

• Coverage Tools

• Design Rule Checker

Design Creation

• HDL Text Editor

Specialty Solutions

• MATLAB/Simulink Co-Simulation
• Verification IP
• HDL Regression Manager

Aldec Webinars

Applications engineers present continuously in live presentation and product demonstrations solutions for current design and verification problems.

Date, topics and content of the events here