Aerospace

Special requirements for aviation and aerospace applications affects the methodology and development of FPGAs. In order to have a common design methodology and a predictable environment which is common to all suppliers and sub suppliers the DO-254 norm was determined.

Some of the challenges for FPGA development:

• Fulfillment of the DO-254 specification norm
• Prototyping of fuse based FPGAs
• To secure the code quality of the development process

Aldec tools:

• DO-254 Development concept supports the clients to fulfill the DO-254 norm
• Actel Protoyping boards and adequate netlist converters
• ALINT rule checker with dedicated DO-254 rule set

DO- 254:

Aldec’s DO-254 CTS (Compliance Tool Set) offers the support of the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED-80) chapter 6.2 “Verification Process” and chapter 11.4 “Tool Assessment and Qualification Process”. The CTS is a fast and secure verification process for the security level A, B, C and D, focused on the increasing hardware testability and the requirement of traceability.

Major CTS Features:

• Design verification within the target device
• In-hardware verification matched to the speed
• Same number of test runs within the target device as simulated with 100% test coverage. Automatic waveform compare between HDL simulation and the result of the hardware test.

The DO-254 “Compliance” verification process is based on the Aldec HDL simulation tool suite. HDL simulation (source level), post-synthesis (gate level) and post place-and-route simulation (timing level), all these tasks are combined in one software environment. The tools suite offers also code-linting, code coverage, profiling, automatic creation of documentation and waveform-comparison.
The simulator uses the test bench developed by the designer to verify the functionality and offers the coverage metric to prove how efficient the design was tested with the test bench. Simulation results will be stored in the waveform format and can automatically compared with the different simulation runs.