Active-HDL Design Flow

The simulation of the design environment ispLever and Diamond from Lattice Semiconductor supports Aldec’s mixed lanquage simulator Active-HDL from ALDEC. Beside the outstanding simulation performance, Active HDL provides a complete design flow manager and comprehensive support for graphical design of VHDL and/or Verilog. Often we got requests for graphical support for the design entry phase thus we offer nowadays a training which deals beside the simulation of VHDL also with graphical entry. Furthermore you will learn to use the modern debugging tools of an integrated design flow. As a special gift every attendee gets a student version of Active HDL. Hence the attendee can repeat at home what he learned and practice to create small block diagrams and state machines.

Pre-Condition:
We strongly recommend the VHDL basic course as pre-condition for the Active-HDL flow training

Dates and Prices

Our regular training dates that are listed on the German page are teached in German language only. Nevertheless we offer all trainings in English on demand. English based trainings can be offered in our regular training center or on side.

For questions about prices, locations and dates please contact us per email .